VLSI Design: Advanced
From silicon engineer to chip architect: SoC microarchitecture, formal verification, advanced timing, low power, DFT, and an AI accelerator tapeout.
- Duration
- 8 weeks
- Level
- Advanced
- Content
- 48 lessons
- 8 modules · 16 h 47 min
- Certificate
- Included
- On completion
- Access
- Fee by email
What you'll learn
Who this course is for
- Intermediate level graduates ready to move into architecture and signoff leadership roles
- Working RTL, verification, or physical design engineers preparing for senior or lead roles
- Engineers who want deep, hands on experience with formal verification and AI hardware design
- Anyone targeting SoC architect, verification lead, physical design lead, or AI hardware engineer roles
Skills you'll gain
This course includes
Course content
8 modules · 48 lessons · 16 h 47 min
SoC architecture and microarchitecture, formal verification and advanced signoff methods, advanced timing variation and signal integrity, low power design at production depth, Design for Test and silicon bring up, a minor project on formal and low power signoff, advanced physical design and tapeout signoff, and a major project architecting and taping out an AI accelerator SoC.
Requirements
- Completion of the Intermediate level, or hands on experience taking RTL through UVM verification, synthesis, and physical design signoff
- Comfort with SystemVerilog, UVM, and physical design concepts
- A computer capable of running advanced EDA tools
About this course
This is the final stage of the Ucanly VLSI Design track, where silicon engineers become chip architects. Built for practitioners with hands on experience taking RTL through UVM verification, synthesis, and physical design signoff, this program goes deep into SoC microarchitecture including pipelines, cache coherence, AMBA CHI, and network on chip design, and formal verification with SVA properties driven to proof convergence. You will master advanced multi corner multi mode static timing analysis, variation aware signoff, and signal integrity, apply low power design at production depth with multi voltage domains and UPF signoff, and build complete Design for Test architectures including scan, MBIST, and post silicon bring up. In your week six minor project, you will run a full formal verification and low power signoff campaign on a complex IP block. You will then move into advanced physical design at modern nodes before your week twelve major project: architecting a complete AI accelerator SoC with a systolic array or dataflow engine, verifying it with UVM and formal methods, optimizing PPA, applying power intent and DFT, and taking it through advanced physical design to full tapeout signoff with a defended architecture specification.
Earn a Ucanly certificate
Complete this course to earn a Ucanly certificate with its own page and QR code. Save it as a PDF, share its link, or add it to the certifications on your LinkedIn profile.
Frequently asked questions
It is recommended, but hands on experience taking RTL through UVM verification, synthesis, and physical design signoff is sufficient to start.
Yes, you will write SVA properties, run formal property verification, drive proofs to convergence, and use formal apps for connectivity and CDC verification, culminating in a full formal and low power signoff campaign.
Yes, your major project is a complete AI accelerator SoC that you architect, verify, optimize, and take through advanced physical design to full tapeout signoff with a defended architecture specification.
Yes, you will receive an Advanced Certificate of Completion from Ucanly once you finish the course.