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Go from zero to your first working silicon design: Verilog, verification, FPGA implementation, and a complete RTL to GDSII ASIC flow.
8 modules · 48 lessons
VLSI and chip design foundations, digital logic fundamentals, Verilog HDL, simulation and verification basics, RTL design of real digital blocks with a protocol controller project, FPGA design and hardware implementation, an introduction to physical design and the ASIC flow, and a major processor design project taken to tapeout ready GDSII.
Kickstart your journey into VLSI and chip design with this beginner friendly program from Ucanly, open to ECE, EEE, CSE, and any engineering graduate with no prior chip design experience. This course takes you from digital logic fundamentals to designing your own RISC processor core and running it through a real open source ASIC flow, with mentor guidance at every step. You will learn Verilog HDL, simulation and self checking testbench verification, and RTL design of real digital blocks including ALUs, memory, and communication protocols like UART, SPI, and I2C. In your minor project in week five, you will design, verify, and deploy a complete protocol controller onto real FPGA hardware. You will then learn FPGA implementation, timing analysis, and an introduction to physical design, before your major project in week eight: architecting your own RISC processor core, running it live on an FPGA, and taking it through the complete RTL to GDSII ASIC flow using OpenLane and the Sky130 PDK to a tapeout ready layout. You will also learn how AI assisted RTL coding and testbench generation are reshaping chip design workflows.
Complete this course to earn a verified Ucanly certificate you can add to your profile, share on LinkedIn, and showcase to employers as proof of the skills you've built.
No, this course is open to ECE, EEE, CSE, and any engineering graduate with no prior chip design experience required.
Yes, your minor project in week five is a protocol controller deployed on real FPGA hardware, and your major project in week eight is your own processor running live on an FPGA and taken through a full ASIC flow to a tapeout ready layout.
Yes, in the major project you will take a design through logic synthesis, floorplanning, placement, routing, static timing analysis, DRC, and LVS using OpenLane and the Sky130 PDK to produce a manufacturable GDSII layout.
Yes, you will receive a Certificate of Completion from Ucanly once you finish the course.