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BeginnerVLSI Design8 weeks
Certificate IncludedCertificate EligibleUcanly certificate

VLSI Design: Beginner

Go from zero to your first working silicon design: Verilog, verification, FPGA implementation, and a complete RTL to GDSII ASIC flow.

Duration
8 weeks
Level
Beginner
Content
48 lessons
8 modules · 15 h 25 min
Certificate
Included
On completion
Access
Fee by email
Or take the free aptitude test

What you'll learn

Explain the complete ASIC and FPGA design flow, from specification to working silicon
Apply digital logic fundamentals including Boolean algebra, Karnaugh maps, and finite state machines
Write synthesizable RTL in Verilog using dataflow, behavioural, and structural modelling
Build self checking testbenches and debug designs using waveforms in GTKWave
Design real digital blocks including ALUs, memory, register files, and UART or SPI communication protocols
Implement designs on FPGA hardware, including synthesis, constraints, and timing closure
Understand logic synthesis, floorplanning, placement, routing, and static timing analysis fundamentals
Architect a RISC processor core and run it live on an FPGA executing real programs
Take a processor design through the complete RTL to GDSII ASIC flow with OpenLane and Sky130 to a tapeout ready layout

Who this course is for

  • ECE, EEE, and CSE engineering students and graduates aiming for a career in VLSI and chip design
  • Absolute beginners who want a clear, guided path into semiconductor design
  • Engineering graduates from other streams looking to enter the semiconductor industry
  • Anyone preparing for VLSI internships and entry level placements in design centres across India

Skills you'll gain

VLSI DesignDigital DesignVerilogSystemVerilogRTL DesignHDLFinite State MachineTestbenchFunctional VerificationFPGAVivadoQuartusModelSimUARTSPITiming AnalysisStatic Timing AnalysisLogic SynthesisPhysical DesignASIC FlowRTL to GDSIIOpenLaneSky130CMOSRISC Processor DesignSemiconductorChip DesignBeginner VLSI

This course includes

Live mentor led Ucanly sessions plus self paced recorded content
On demand video lectures with downloadable source code for every lesson
A minor project running on real FPGA hardware by week five
A major project taken through the complete RTL to GDSII ASIC flow by week eight
Guided portfolio and project positioning for placements and internships
Lifetime access to course materials and future updates
Certificate of Completion from Ucanly

Course content

8 modules · 48 lessons · 15 h 25 min

VLSI and chip design foundations, digital logic fundamentals, Verilog HDL, simulation and verification basics, RTL design of real digital blocks with a protocol controller project, FPGA design and hardware implementation, an introduction to physical design and the ASIC flow, and a major processor design project taken to tapeout ready GDSII.

Requirements

  • A computer (Windows, macOS, or Linux) capable of running EDA simulation tools
  • No prior chip design experience required, open to ECE, EEE, CSE, and any engineering graduate
  • Basic comfort with digital logic concepts is helpful but not required
  • Curiosity, consistency, and a willingness to build things by doing

About this course

Kickstart your journey into VLSI and chip design with this beginner friendly program from Ucanly, open to ECE, EEE, CSE, and any engineering graduate with no prior chip design experience. This course takes you from digital logic fundamentals to designing your own RISC processor core and running it through a real open source ASIC flow, with mentor guidance at every step. You will learn Verilog HDL, simulation and self checking testbench verification, and RTL design of real digital blocks including ALUs, memory, and communication protocols like UART, SPI, and I2C. In your minor project in week five, you will design, verify, and deploy a complete protocol controller onto real FPGA hardware. You will then learn FPGA implementation, timing analysis, and an introduction to physical design, before your major project in week eight: architecting your own RISC processor core, running it live on an FPGA, and taking it through the complete RTL to GDSII ASIC flow using OpenLane and the Sky130 PDK to a tapeout ready layout. You will also learn how AI assisted RTL coding and testbench generation are reshaping chip design workflows.

Earn a Ucanly certificate

Complete this course to earn a Ucanly certificate with its own page and QR code. Save it as a PDF, share its link, or add it to the certifications on your LinkedIn profile.

Certificate IncludedCertificate EligibleUcanly certificate

Frequently asked questions

No, this course is open to ECE, EEE, CSE, and any engineering graduate with no prior chip design experience required.

Yes, your minor project in week five is a protocol controller deployed on real FPGA hardware, and your major project in week eight is your own processor running live on an FPGA and taken through a full ASIC flow to a tapeout ready layout.

Yes, in the major project you will take a design through logic synthesis, floorplanning, placement, routing, static timing analysis, DRC, and LVS using OpenLane and the Sky130 PDK to produce a manufacturable GDSII layout.

Yes, you will receive a Certificate of Completion from Ucanly once you finish the course.