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IntermediateVLSI Design8 weeks
Certificate IncludedCertificate EligibleUcanly certificate

VLSI Design: Intermediate

Go from RTL coder to silicon engineer: advanced SystemVerilog, UVM verification, AMBA protocols, synthesis, timing closure, low power, and DFT.

Duration
8 weeks
Level
Intermediate
Content
48 lessons
8 modules · 16 h 25 min
Certificate
Included
On completion
Access
Fee by email
Or take the free aptitude test

What you'll learn

Write advanced SystemVerilog with interfaces, packages, and parameterized reusable architecture
Handle clock domain crossing and metastability in real designs
Build constrained random, coverage driven testbenches with SystemVerilog assertions
Architect complete UVM environments with agents, sequences, scoreboards, and the UVM factory
Verify AMBA APB, AHB, and AXI protocol interfaces and build protocol VIP
Design SoC subsystems, integrate IP, and drive logic synthesis with professional SDC constraints
Perform static timing analysis, close timing violations, and apply low power design with UPF
Insert Design for Test structures including scan chains and ATPG
Take a multi block SoC subsystem from SystemVerilog RTL through UVM signoff to a signed off GDSII

Who this course is for

  • Beginner level graduates ready to move into professional design or verification roles
  • Engineers with FPGA or basic RTL experience wanting structured, industry standard skills
  • Engineering graduates preparing for RTL, verification, or physical design interviews
  • Anyone who wants hands on experience with UVM and a full RTL to GDSII SoC flow

Skills you'll gain

Intermediate VLSISystemVerilogUVMFunctional VerificationConstrained Random VerificationFunctional CoverageSystemVerilog AssertionsAMBAAXIAPBAHBProtocol VerificationSoC DesignIP IntegrationLogic SynthesisSDC ConstraintsStatic Timing AnalysisTiming ClosureClock Tree SynthesisLow Power DesignUPFClock GatingDFTScan ChainATPGPhysical DesignRTL to GDSIIOpenLaneSky130Silicon Engineer

This course includes

Live mentor led Ucanly sessions plus self paced recorded content
A minor project building a complete UVM verification environment by week five
A major project taking an SoC subsystem from RTL to signed off GDSII by week ten
Ucanly portfolio review, mock RTL, verification and physical design interviews, and a personalized roadmap to Advanced
Lifetime access to course materials and future updates
Certificate of Completion from Ucanly

Course content

8 modules · 48 lessons · 16 h 25 min

Advanced SystemVerilog for design, functional verification and SystemVerilog testbenches, UVM the industry verification standard, protocol verification with AMBA interfaces, a minor project building a full UVM environment, SoC design and logic synthesis, static timing analysis low power and DFT, and a major project taking an SoC subsystem from RTL to signed off GDSII.

Requirements

  • Completion of the Beginner level, or working knowledge of Verilog, testbenches, FPGA implementation, and basic synthesis and timing
  • A computer capable of running EDA simulation and synthesis tools
  • Comfort writing and debugging RTL and testbenches

About this course

Level up from RTL coder to silicon engineer. This intermediate program from Ucanly takes practitioners with working knowledge of Verilog, testbenches, FPGA implementation, and basic synthesis and timing into professional design and verification: advanced SystemVerilog with interfaces, clock domain crossing, and parameterized reusable architecture, constrained random and coverage driven verification, and the full UVM methodology used across the semiconductor industry. You will verify real AMBA protocols including APB, AHB, and AXI, then build a complete UVM verification environment from scratch in your week five minor project, driven to full functional and code coverage closure. You will move into SoC design and logic synthesis, static timing analysis and timing closure, low power design with UPF, and Design for Test with scan chains and ATPG. You will graduate having taken a multi block SoC subsystem through your week ten major project: SystemVerilog RTL, UVM signoff, synthesis, low power intent, DFT insertion, and full physical design to a timing clean, DRC clean, and LVS clean GDSII.

Earn a Ucanly certificate

Complete this course to earn a Ucanly certificate with its own page and QR code. Save it as a PDF, share its link, or add it to the certifications on your LinkedIn profile.

Certificate IncludedCertificate EligibleUcanly certificate

Frequently asked questions

It is recommended, but working knowledge of Verilog, testbenches, FPGA implementation, and basic synthesis and timing is sufficient to start.

Yes, your minor project in week five is a complete UVM verification environment built from scratch for an AMBA protocol block, driven to full functional and code coverage closure.

Yes, your major project takes a multi block SoC subsystem from SystemVerilog RTL through UVM verification, synthesis, low power design, DFT insertion, and physical design to a signed off GDSII.

Yes, you will receive a Certificate of Completion from Ucanly once you finish the course.