VLSI Design: Advanced
From silicon engineer to chip architect: SoC microarchitecture, formal verification, advanced timing, low power, DFT, and an AI accelerator tapeout.
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- Advanced
- 8 weeks
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From silicon engineer to chip architect: SoC microarchitecture, formal verification, advanced timing, low power, DFT, and an AI accelerator tapeout.
Go from RTL coder to silicon engineer: advanced SystemVerilog, UVM verification, AMBA protocols, synthesis, timing closure, low power, and DFT.
Go from zero to your first working silicon design: Verilog, verification, FPGA implementation, and a complete RTL to GDSII ASIC flow.
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